Efficient Deep Neural Networks Architecture for Video Analytics Systems

Engineer at Lowes

Spiking Neural Network Architectures

Engineer at AMD

Efficient Deep Neural Networks Architecture for Video Analytics Systems

Engineer at Lowes

Design of processing-in-memory architectures for deep learning and graph

Engineer at Nvidia

Non-volatile memory design based on crossbar architecture towards low power systems and processing in-memory

AMD

Technology Driven Architecture Support for Memory Hierarchies

Assistant Professor, North Dakota State University

Context-Aware Design and Optimization of Embedded Deep Neural Network Architectures

Microsoft Corporation

Self-Powered Neuromorphic Vision Processors

Winner of EDAA Outstanding Dissertation Award and the China Overseas Talent and Innovation Entrepreneur based on innovation resulting from Ph.D. Research and co-founded PI2Star

Assistant Professor in Tsinghua University

Large-scale object recognition for embedded wearable platforms

Winner of 2013 Richard Newton Young Fellowship Program

Senior Hardware Engineer at Samsung Research America.

Developing key hardware technology for next generation Samsung Mobile products. 

Design and Exploration of Accelerator-rich Multi-core Systems

Research Staff Member, IBM Watson Research Labs.

Her work, funded by the DARPA PERFECT program, consists of examining techniques for reliable operation at very low voltages and designing a chip to establish proof of concept.

She is also involved in developing pre-RTL optimization tools for modeling power, performance and reliability to aid IBM product transitions.  

Data dependent optimization vision architecture

Game Software Designer

Enabling intelligent vision systems in a configurable multi-algorithm pipeline

Research Engineer, Applied Research Labs, Penn State

Using attention to enhance efficiency in video-based computer systems

Senior R&D Engineer, Synopsys Inc

Contributed to physical placer development and optimization for the new generation of Design Compiler, the industry leading tool for logic synthesis

Modeling, circuit design, and microarchitectural optimization of emerging resistive memory

Research Engineer at Hewlett Packard Labs

Acceleration of deep learning workloads on Moonshot servers with integrated GPUs 

Configurable accelerators for visual and text analytics

Machine Learning Engineer, Intel, Santa Clara

System-on-Chip integration of heterogeneous accelerators for perceptual computing

Hardware Design Engineer, Intel, Folsom

Accelerating design and implementation of embedded vision systems

Assistant Professor at Sultan Qaboos University, Oman (premiere university in Oman)

Appointed as a member of the National Committee for Approving Programs for all universities in Oman. Founder and Chair of the IEEE Computer Society in Oman. 

Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems

Senior Researcher at Electronics and Telecommunications Research Institute (ETRI), Taiwan

Involved with design of neuromorphic hardware accelerators and embedded systems

Configurable accelerators for video analytics

Research Staff Member at IBM Almaden Research Center

IBM Corporate Award for Development of Cryptographic Hardware Module for System Z Mainframe (used by 96% of the banks around the world). Recipient of Misha Mahowald prize for Neuromorphic Engineering (TrueNorth), one of the first commercial neuromorphic chips in the world.

Device and architecture co-design for ultra-low power logic using emerging tunneling-based devices

Staff Software Engineer, Intel, Santa Clara

Develops RTL2GDS methodologies intended to reduce the impact of parasitic on timing convergence of SoC blocks

Towards minimizing the adverse effects of temperature on high performance digital systems

Graphics Hardware Engineer at Intel, Folsom, CA

Responsible for the RTL verification and development for various codecs including the encode and decode of HEVC and VP9 

Influence of emerging technologies on interconnect architectures

Component Design Engineer, Intel, Santa Clara

Performance Architect for server platforms

Analysis of failures in nanoscale devices

Section Manager at TSMC Taiwan

Test Chip Design and Development Division. Incharge of test-chip design team for TSMC internal test-chips and customer test chips. Owns 4 patents.

Closing the gap between FPGA and ASICS: The applications of clock skew scheduling on FPGAs

CAD Software Engineer at Intel Santa Clara

A configurable platform for sensor and image processing

Founder SiliconScapes, LLC

Silicon Scapes produces custom accelerators for Defense and Commercial applications. Siliconscapes emerged from a Ben Franklin TechCelerator @State College award to transition research to commercial products.

High-performance signal processing on reconfigurable platforms

Principal Engineer, Samsung, Korea

Research and Development of next generation television systems.

Secure communications in sensor networks

Software Engineer at Intel Corporation, Phoenix

Have designed, developed, and evaluated highly complex cryptosystems, including eventual release into multiple products.  Served as secure boot architect for Intel’s 2014 tablet product.

Soft errors in logic circuits: Analysis and modeling

Component Design Engineer, Intel, Bangalore

Tackling power and reliability issues in field programmable gate arrays

Founded Gnoll Technologies Pvt. Ltd

a company excelling in the most advanced IOT solutions. an entrepreneur (Gnoll Technologies Pvt. Ltd.) and Senior Vice President of a joint venture of his company with a multi-million dollar firm(yet to be public) developing hardware and software integrated IOT solutions catering to numerous industries. In past, lead the performance and power analysis team of ARM, the front face to all ARM IP going out to partners for 4 years and before that worked with Intel Labs and Design teams for 5 years, on their future products. He owns the patent for the current world’s best circuit for True Random Number Generator (digital) and the fastest Floating Point MAC Algorithm, both implemented in Intel’s main core

Implications of future technologies on the design of FPGAs

Senior Software Engineer, Xilinx, Hyderabad

Developed Vivado physical synthesis, a leading FPGA design tool in industry, from the ground up. Architected the solution. Developed incremental placement algorithm and timing optimizations.

Efficient VLSI architectures for image and video signal processing algorithms

Associate Professor, Department of Electronic and Electrical Engineering, Sejong Campus, Hongik University, South Korea

Temperature -aware computing

Manager, Embedded Software, Magic Leap

Defining and implementing linux kernel module interfaces. High performance embedded framework design and implementation, including hard timing constraints. Internal team support.

Soft errors: Modeling and interactions with power optimizations

Principal Engineer, Intel

ServedSOC and Power Architect for Intel’s mainstream Client microprocessors. For the past 12 years, Vijay is responsible in making several generations of Intel CoreTM products to have lower power and longer battery life.

Designing energy-efficient and reliable caches and interconnects

Staff Engineer, Qualcomm, North Carolina

Processor and system performance modeling and analysis

Orchestrating the compiler and microarchitecture for reducing cache energy

DataCenter Power Management Technologist, Intel, Santa Clara

40+ publications and one patent. Sets the enabling strategy for power management at silicon & platform levels. Provides leadership role in the resolution of major customer power management issues & requirements

Energy -efficient high performance cache architectures

Associate Professor at KAIST, premier institution in Korea

Winner of multiple best paper awards and the 2015 KAIST 10 best research accomplishment for work on small Drone-detecting RADAR. His students are faculty members in Pakistan and Bangladesh and at IBM Watson Research Center in USA. 

Optimizing privacy preserving neural networks employing homomorphic encryption.

Optimizing existing NLP tasks by employing Knowledge Graphs Knowledge Graph Embedding.

Extending Video Action Recognition in the Compressed Domain Video Analytics in Compressed Domain. 

Hardware Functional Obfuscation With Ferroelectric Active Interconnects.

AIGuide : An Augmented Reality Hand Guidance Application for People with Visual Impairments

Optimization of Inter-Cache Traffic Entanglement in Tagless Caches with Tiling Opportunities. 

Using a UAV and Edge Computing to Identify and Throw Away Trash.

A Processing-in-Memory Accelerator Architecture for Graph Analytics

Sensor Aware Machine Learning for Edge Devices

Context-Aware Collaborative Object Recognition for Multi Camera Time Series Data.

Collaborative Inference for Distributed Camera System

Employing Text Features for Visual Assistance in Navigation and Classification. 

Designing Processing in Memory Architectures Via Static Analysis on Real Programs.

Hardware Acceleration of Visual Search.   

Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor

Senior Software Engineer, Visa Inc., Austin

A platform for evaluating embedded multi-core systems.

Verification Engineer, Intel, Phoenix.

A Reconfigurable Accelerator For Neuromorphic Object Recognition.

Staff Embedded Systems Designer, Edwards Lifesciences, Orange County, CA 

A High-efficiency Switched-capacitance Htfet Charge Pump For Low-input-voltage Applications.

Software Engineer, Google

Optimization and Hardware Acceleration of Consensus-based Matching and Tracking.

Embedded Systems Engineer, Philips Respironics, PA. 

Depth Estimation using monocular cameras.

Component Design Engineer, Intel, Folsom.

Image processing using coupled oscillators.

Senior Imaging Engineer, GEO Semiconductor Inc, Bay Area. 

Tunnel FET based Field Programmable Gate Arrays.

Intel India

A Fine-Grained Dataflow Library for Reconfigurable Streaming Accelerators

Logic Design Engineer, Intel, Folsom

FPGA based Image recognition

Connected Component Labeling on FPGAs

IP Logic Designer at Intel

A Neural Network Based Classifier on Cell Broadband Engine.

Computational Scientist, Virginia Tech

A Signal Based Approach to an Instrument Driver System

Performance-Reliability Tradeoffs in designing reorder buffers.

Senior Software Engineer at Google

Impact of Circuit Degradation on Design Security of Field programmable Devices.

Intellectual Property Attorney, Perkins Coie LLP 

Performance Evaluation of SystemC and Verilog for RTL Synthesis and System Modeling

MBA Candidate. Worked for Intel as first job after graduation. 

Mapping Signal Processing Applications on FPGAs

Hardware Design Engineer at HCL America, Rochester

On-Chip Interconnects.

Embedded Face Detection

Soft error analysis of CAMs

Test R&D Engineer at Intel Corporation, Oregon

Encryption and Security in SRAM FPGAs

Senior Principal Systems Engineer / Software Development Lead at General Dynamics Information Technology

Analyzing the Common Language Runtime

Variable Line Sized Cached DRAM

VP, Architecture at J.P. Morgan, New York

Characterization and Modeling for Run-time Leakage Reduction Techniques

Evaluating Energy-Efficiency of Channel Coders

OS Paging Issues for DRAM Energy Management

Memory Energy: Modeling and Optimizations

Implementation of a Java Accelerator:  Interfacing the Java Virtual Machine with the FPGA

Senior Application Engineer, Accenture

Influence of MPEG-4 Parameters on System Energy

R&D Manager at Synopsys

Low Power Content Addressable Memory Design

Primary Patent Examiner, USPTO

Power Modeling and Optimization of Memories and Functional Units

Co-Founder, CEO at AVAtronics, Switzerland

Protecting Java Applications Against Decompilation via Control Flow Obfuscation

Vice-President, Enterprise Architect, PNC, Pittsburgh

Annotation Based Energy Optimization for Java

Enterprise Architect, Dell

Haptic Feedback System for Percussive Elements in Music

Detecting and Tracking Insects in the InsectEye Device

Addressing Overfitting Issues with Deep Learning Model for Video Action Recognition

Attention-Based Human Activity Recognition

The Accuracy of Rhythm Recognition with Convolutional Neural Networks on TrueNorth Processor

Comparing Integrate And Fire Neuron Circuits Using TFET And CMOS Technologies

Network-on-chip router design 

Exploring the impact of soft-errors on memory cell design

A remote execution framework for an embedded Java environment

Design of a databus charge recovery mechanism

Founder of EDAPlayground (Acquired by Doulous) and mdPortal

Assistant Professor. Capital Normal University, Beijing

Assistant Professor. Xidian University

Assistant Professor, Sivan Nadar University, India

Researcher, Toshiba, Japan

 IBM Research

Intel 

Professor, IIT Madras, India

South Bend, IN

Tyrone Area HS

Grier School

Tyrone Area HS

Tyrone Area School District

Grier School for Girls