Overview:
The field of artificial intelligence (AI) has recently made significant strides, with notable advancements such as large language models like ChatGPT taking the world by storm. However, these breakthroughs would not have been possible without the availability of powerful computing hardware, such as graphics processing units (GPUs). Such hardware has benefited from several decades of technology scaling following Moore’s law. As technology approaches its physical limits and AI models require exponentially increasing hardware resources, including computation and storage, alternative computing paradigms with superior energy efficiency and performance are necessary for a sustainable future. Compute-in-memory is one promising approach where computations are directly performed in memory units, eliminating most data movements, a key bottleneck in conventional computers. However, to best exploit the compute-in-memory for acceleration of AI models on the scale of giga-byte to tera-byte levels, it is critical to have high capacity, energy-efficient, and high performance memory technology to fit the models. NAND memory is a form of erasable programmable read-only memory that takes its name from the not-and (NAND) logic gate. The proposed research aims to develop ferroelectric vertical NAND memory to meet these demands and at the same time train students for developing a future workforce for the semiconductor industry.
Vertical NAND memory offers the highest density by increasing the number of stacked layers vertically. However, conventional vertical NAND memory based on floating gate or charge trap flash suffers from poor performance, including high write voltage, low speed, and poor endurance, despite their large capacity. To address these issues, this research proposes the development of a vertical NAND flash alternative: the vertical NAND ferroelectric field-effect transistor (FeFET), which achieves high density and high performance simultaneously. By leveraging the recently discovered ferroelectric HfO2, superior performance can be achieved as ferroelectric programming is driven by an applied electric field, which can be energy-efficient and fast. The project aims to design and evaluate vertical NAND FeFET-based compute-in-memory accelerators from devices to architectures, with innovations such as novel cell designs to achieve multi-level cell and variation suppression, vertical NAND array disturb mitigation with a novel array structure, and mapping and benchmarking of various important information processing tasks to the vertical NAND FeFET array. Additionally, this research includes workforce training activities such as lectures and hands-on experience offered to K-12 students and teachers to promote excitement and attract them to the talent pipeline for the semiconductor industry. The proposed research will recruit graduate and undergraduate students via the Research Experience for Undergraduates (REU) program from underrepresented groups, and the knowledge acquired in this project will be distributed through curriculum development and online sharing repositories.
